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k4s643233e-se(n) cmos sdram - 1 - rev. 1.4 (nov. 2001) 2m x 32 sdram revision 1.4 november 2001 512k x 32bit x 4 banks synchronous dram lvttl(3.0v & 3.3v) samsung electronics reserves the right to change products or specification without notice. extended temperature tsop / 90ball fbga (v dd /v ddq 3.0v/3.0v, 3.3v/3.3v)
k4s643233e-se(n) cmos sdram - 2 - rev. 1.4 (nov. 2001) revision 1.4 (november 15, 2001) - final ? final specification for 2mx32 sdram. revision 1.3 (october 10, 2001) - preliminary ? integrated 3.0v part numbr(k4s643234e-s(t)e(n)) and 3.3v part number(k4s643232e-s(t)e(n)) to 3.0v & 3.3v part- number(k4s643233e-s(t)e(n)). ? deleted tcc 5ns part and 6ns part. ? unification of tch 3ns for -70 part and tch 3ns for -80 part, tch 3ns for -10 part. ? unification of tcl 3ns for -70 part and tcl 3ns for -80 part, tcl 3ns for -10 part. ? unification of tss 1.75ns for -70 part and tss 2ns for -80 part, tss 2.5ns for -10 part. ? changed tcdl form 2clk to 1clk and trdl for cl1 from 1clk to 2clk. revision 1.2 (august 7, 2001) - target ? added cas latency 1 revision 1.1 (july 6, 2001) ? added k4s643232e-t/s(e/n)50 revision 1.0 (april 6, 2001) revision 0.0 (march 21, 2001) ? initial draft ? extended temperature (-25 c ~ 85 c ) ? 3.3v power supply (vdd &vddq) ? supported 90-ball fbga as well as 86 - tsop revision history
k4s643233e-se(n) cmos sdram - 3 - rev. 1.4 (nov. 2001) the k4s643233e is 67,108,864 bits synchronous high data rate dynamic ram organized as 4 x 524,288 words by 32 bits, fabricated with samsung s high performance cmos technol- ogy. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ? 3.0v & 3.3v power supply ? lvttl compatible with multiplexed address ? four banks operation ? mrs cycle with address key programs -. cas latency (1 & 2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? burst read single-bit write operation ? dqm for masking ? auto & self refresh ? 64ms refresh period (4k cycle). ? extended temperature range : -25 o c to +85 o c. general description features 512k x 32bit x 4 banks synchronous dram ordering information ? - s(t)e/n : extended temperature (-25 o c - 85 o c) part no. max freq. interface package k4s643233e-se/n70 143mhz lvttl 90-ball fbga k4s643233e-se/n80 125mhz k4s643233e-se/n10 100mhz k4s643233e-te/n70 143mhz 86 tsop(ii) k4s643233e-te/n80 125mhz k4s643233e-te/n10 100mhz functional block diagram samsung electronics reserves the right to change products or specification without notice. * bank select data input register 512k x 32 512k x 32 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we dqm lwe ldqm dqi clk add lcas lwcbr 512k x 32 512k x 32 timing register
k4s643233e-se(n) cmos sdram - 4 - rev. 1.4 (nov. 2001) pin configuration (top view) v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 n.c v dd dqm0 we cas ras cs n.c ba0 ba1 a10/ap a0 a1 a2 dqm2 v dd n.c dq16 v ssq dq17 dq18 v ddq dq19 dq20 v ssq dq21 dq22 v ddq dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 n.c v ss dqm1 n.c n.c clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss n.c dq31 v ddq dq30 dq29 v ssq dq28 dq27 v ddq dq26 dq25 v ssq dq24 v ss 86pin tsop (ii) (400mil x 875mil) (0.5 mm pin pitch) 86 - tsop
k4s643233e-se(n) cmos sdram - 5 - rev. 1.4 (nov. 2001) 90ball(6x15) csp 1 2 3 7 8 9 a dq26 dq24 v ss v dd dq23 dq21 b dq28 v ddq v ssq v ddq v ssq dq19 c v ssq dq27 dq25 dq22 dq20 v ddq d v ssq dq29 dq30 dq17 dq18 v ddq e v ddq dq31 nc nc dq16 v ssq f v ss dqm3 a3 a2 dqm2 v dd g a4 a5 a6 a10 a0 a1 h a7 a8 nc nc ba1 nc j clk cke a9 ba0 cs ras k dqm1 nc nc cas we dqm0 l v ddq dq8 v ss v dd dq7 v ssq m v ssq dq10 dq9 dq6 dq5 v ddq n v ssq dq12 dq14 dq1 dq3 v ddq p dq11 v ddq v ssq v ddq v ssq dq4 r dq13 dq15 v ss v dd dq0 dq2 pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 10 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable dqm 0 ~ dqm 3 data input/output mask dq 0 ~ 31 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground 90-ball fbga package dimension and pin configuration < bottom view *1 > < top view *2 > < top view *2 > *2: top view symbol min typ max a - 1.40 1.45 a 1 0.30 0.35 0.40 e - 11.00 - e 1 - 6.40 - d - 13.00 - d 1 - 11.20 - e - 0.80 - j b 0.40 0.45 0.50 z - - 0.10 [unit:mm] 5 2 1 6 3 4 8 9 7 f e d c b j h g a e d d / 2 d 1 e 1 e e/2 a a1 z j b substrate(4layer) k 4 s 6 4 3 2 3 3 e s a m s u n g w e e k #a1 ball origin indicator *1: bottom view m l k r p n
k4s643233e-se(n) cmos sdram - 6 - rev. 1.4 (nov. 2001) dc operating conditions ? recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 o c to +85 o c) parameter symbol min typ max unit note supply voltage v dd , v ddq 2.7 3.0 3.6 v input logic high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 1. v ih (max) = 5.6v ac.the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq , input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. notes : absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref = 1.4v 200 mv) pin symbol min max unit clock c clk - 4 pf ras , cas , we , cs , cke, dqm c in - 4.5 pf address c add - 4.5 pf dq 0 ~ dq 31 c out - 6.5 pf
k4s643233e-se(n) cmos sdram - 7 - rev. 1.4 (nov. 2001) (recommended operating condition unless otherwise noted, t a = -25 o c to +85 o c) parameter symbol test condition cas latency speed unit note -70 -80 -10 operating current (one bank active) i cc1 burst length =1 t rc 3 t rc (min), t cc 3 t cc (min), io = 0ma 155 150 140 ma 2 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 15ns 3 ma i cc2 ps cke & clk v il (max), t cc = 2 precharge standby current in non power-down mode i cc2 n cke 3 v ih(min) , cs 3 v ih(min) , t cc = 15ns input signals are changed one time during 30ns 20 ma i cc2 ns cke 3 v ih(min) , clk v il(max) , tcc = input signals are stable 10 active standby current in power-down mode i cc3 p cke v il(max), t cc = 15ns 7 ma i cc3 ps cke v il(max) , t cc = 5 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih(min) , cs 3 v ih(min) , t cc = 15ns input signals are changed one time during 30ns 55 ma i cc3 ns cke 3 v ih(min) , clk v il(max) , t cc = input signals are stable 40 operating current (burst mode) i cc4 io = 0 ma, page burst all bank activated, t ccd = t ccd(min) 170 160 150 ma 2 refresh current i cc5 t rc 3 t rc(min) 165 155 145 ma 3 self refresh current i cc6 cke 0.2v -s(t)e 3 ma 4 -s(t)n 450 ua 5 dc characteristics 1. unless otherwise notes, input level is cmos(v ih /v il =v ddq /v ssq ). 2. measured with outputs open. 3. refresh period is 64ms. 4. k4s643233e-s(t)e** 5. k4s643233e-s(t)n** notes :
k4s643233e-se(n) cmos sdram - 8 - rev. 1.4 (nov. 2001) ac operating test conditions (v dd = 2.7v ~ 3.6v , t a = -25 o c to +85 o c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 vddq 1200 w 870 w output 30pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 30pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note -70 -80 -10 cas latency cl 3 2 1 3 2 1 3 2 1 clk clk cycle time t cc(min) 7 10 20 8 12 20 10 12 20 ns row active to row active delay t rrd(min) 2 2 1 2 2 1 2 2 1 clk 1 ras to cas delay t rcd(min) 3 2 1 3 2 1 2 2 1 clk 1 row precharge time t rp(min) 3 2 1 3 2 1 2 2 1 clk 1 row active time t ras(min) 7 5 2 6 4 2 5 4 2 clk 1 t ras(max) 100 us row cycle time t rc ( min ) 10 7 3 10 7 3 10 7 3 clk 1 last data in to row precharge t rdl(min) 2 clk 2 last data in to new col.address delay t cdl(min) 1 clk 2 last data in to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1 clk 3 mode register set cycle time t mrs(min) 2 clk number of valid output data cas latency=3 2 ea 4 cas latency=2 1 cas latency=1 0 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. notes :
k4s643233e-se(n) cmos sdram - 9 - rev. 1.4 (nov. 2001) 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. note : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -70 -80 -10 unit note min max min max min max clk cycle time cas latency=3 t cc 7 1000 8 1000 10 1000 ns 1 cas latency=2 10 12 12 cas latency=1 20 20 20 clk to valid output delay cas latency=3 t sac - 5.5 - 6 - 6 ns 1, 2 cas latency=2 - 6 - 8 - 8 cas latency=1 - 18 - 18 - 18 output data hold time cas latency=2,3 t oh 2 - 2 - 2 - ns 2 cas latency=1 3 - 3 - 3 - clk high pulse width t ch 3 - 3 - 3.5 - ns 3 clk low t cl 3 - 3 - 3.5 - ns 3 input setup time t ss 1.75 - 2 - 2.5 - ns 3 input hold time t sh 1 - 1 - 1 - ns 3 clk to output in low-z t slz 1 - 1 - 1 - ns 2 clk to output in hi-z cas latency=3 t shz - 5.5 - 6 - 6 ns - cas latency=2 - 6 - 8 - 8 cas latency=1 - 18 - 18 - 18
k4s643233e-se(n) cmos sdram - 10 rev. 1.4 (nov. 2001) simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap , a 9 ~ a 0 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~ a 7 ) 4 auto precharge enable h 4,5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~ a 7 ) 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 10 & ba 0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) notes : x
k4s643233e-se(n) cmos sdram - 11 rev. 1.4 (nov. 2001) mode register field table to program modes register programmed with mrs address function a 10 /ap rfu a 9 w.b.l a 8 a 7 tm a 6 a 5 a 4 a 3 a 2 a 1 a 0 cas latency bt burst length a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 bt = 0 test mode type mode register set reserved reserved reserved 0 0 1 1 0 1 0 1 write burst length a 9 0 1 length burst single bit latency reserved 1 2 3 reserved reserved reserved reserved cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 burst type 0 1 bt = 1 burst length type sequential interleave 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 reserved reserved reserved full page 1 2 4 8 reserved reserved reserved reserved power up sequence sdrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and start clock. must maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. power is applied to vdd and vddq (simultaneously). 3. maintain stable power, stable clock and nop input condition for a minimum of 200us. 4. issue precharge commands for all banks of the devices. 5. issue 2 or more auto-refresh commands. 6. issue a mode register set command to initialize the mode register. cf.) sequence of 4 & 5 is regardless of the order. the device is now ready for normal operation. note : 1. if a 9 is high during mrs cycle, "burst read single bit write" function will be enabled. 2. rfu (reserved for future use) should stay "0" during mrs cycle. full page length : x32 (256) ba 0 ~ ba 1 rfu
k4s643233e-se(n) cmos sdram - 12 rev. 1.4 (nov. 2001) burst sequence (burst length = 4) initial address sequential interleave a 1 a 0 0 0 1 1 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 burst sequence (burst length = 8) initial address sequential interleave 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 2 3 4 5 6 7 0 1 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 a 1 a 0 a 2 0 0 1 1 0 0 1 1 1 2 3 4 5 6 7 0 3 4 5 6 7 0 1 2 5 6 7 0 1 2 3 4 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 2 3 0 1 6 7 4 5 4 5 6 7 0 1 2 3 6 7 4 5 2 3 0 1 1 0 3 2 5 4 7 6 3 2 1 0 7 6 5 4 5 4 7 6 1 0 3 2 7 6 5 4 3 2 1 0

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